Modern computer networks can communicate at very high data rates. Local Area Networks (LAN) and Wide Area Network (WAN) can transmit and receive hundreds of millions of bits per second over a single cable. Optically linked networks can communicate far faster, taxing the abilities of the even fastest processors.
Maintaining accurate reception of signals transmitted in high speed networks requires that extremely accurate clocks be in synchrony at each end of a communication. Because different transmitters and receivers are located at different distances away from each other, and the amount of time to travel any length of cable varies, received data clock “ticks' can drift away from a receiver's clock. Hence, clock signals are necessarily inherent in data signals.
Data transmission densities, the bit rates that are transmitted on any network cable, vary with data content, time, distance, hardware and other constraints. A receiver may have to adapt to data densities that can vary by a factor of 20 or more. Since a transition between high and low voltages is the readable feature in a data stream, data densities are best expressed as data transition density, or DTD.
There are processes in existence in which receivers can attempt to keep pace with changing DTDs. Such processes are known as Clock and Data Recovery or CDR.
CDRs can be required to receive input data whose average transition density, TD, can vary from five to one hundred percent of the maximum available rate. In other words, DTD, as well as the loop gain at the receiver, can vary by a factor of twenty. In a typical Phase-Locked Loop (PLL) CDR design, it is difficult to have Clock and Data Recovery meet the Synchronous Optical Network (SONET) jitter transfer specification with 20 times DTD, especially in light of variations in process, supply voltage and temperature, or PVT.
There are a number of ways by which solving this problem has been attempted. One way is to limit DTD variations in the input data or use external components to reduce PVT variations. Another one is to have loop gain compensated. Existing architectures use a counter to count VCO clock cycles between adjacent data transitions. The lower the DTD, the more clock cycles will be counted. The counter generates control voltages which adjust charge pump gain to compensate DTD variation.
In U.S. Pat. No. 5,315,270 issued May 24, 1994, to Leonowich, the loop gain of a phase locked loop is made to be controllably responsive to the transition density of an input data signal. In one embodiment a charge pump, positioned between the phase detector and the loop filter, supplies pulse-amplitude-modulated current pulses to the loop filter, the amplitude of pulses being related to the data transition density.
However, schemes such as that described in the cited patent cannot used with different linear phase detectors and are prone to lock into harmonics in the data stream. Further, they are necessarily higher speed devices and can generate high switching noise, implying high jitter, as well as consume higher power.